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https://github.com/steveicarus/iverilog.git
synced 2026-09-08 04:20:49 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
34 lines
667 B
VHDL
34 lines
667 B
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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package work14_pkg is
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function f_log2_size (
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A : natural)
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return natural;
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component work14_comp
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generic (
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max_out_val : natural;
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sample_parm : string);
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port (
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clk_i : in std_logic;
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val : out std_logic_vector(f_log2_size(max_out_val)-1 downto 0));
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end component;
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end work14_pkg;
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package body work14_pkg is
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function f_log2_size (A : natural) return natural is
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begin
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for I in 1 to 64 loop -- Works for up to 64 bits
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if (2**I >= A) then
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return(I);
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end if;
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end loop;
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return(63);
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end function f_log2_size;
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end work14_pkg;
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