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https://github.com/steveicarus/iverilog.git
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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
31 lines
557 B
VHDL
31 lines
557 B
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.work14_pkg.all;
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entity work14_comp is
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generic (
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max_out_val : natural := 3;
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sample_parm : string := "test");
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port (
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clk_i : in std_logic;
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val : out std_logic_vector(f_log2_size(max_out_val)-1 downto 0));
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end work14_comp;
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architecture rtl of work14_comp is
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begin -- rtl
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foo : process(clk_i)
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begin
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if rising_edge(clk_i) then
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val <= std_logic_vector(to_unsigned(max_out_val, val'length));
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end if;
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end process;
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end rtl;
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