mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-09-03 01:43:14 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
84 lines
1.5 KiB
Verilog
84 lines
1.5 KiB
Verilog
module main;
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reg a, b;
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triand net;
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assign net = a;
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assign net = b;
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initial begin
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a = 'b0;
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b = 'b0;
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#1 if (net !== 1'b0) begin
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$display("FAILED -- a=%b, b=%b, net=%b", a, b, net);
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$finish;
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end
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a = 'b0;
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b = 'b1;
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#1 if (net !== 1'b0) begin
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$display("FAILED -- a=%b, b=%b, net=%b", a, b, net);
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$finish;
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end
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a = 'b0;
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b = 'bx;
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#1 if (net !== 1'b0) begin
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$display("FAILED -- a=%b, b=%b, net=%b", a, b, net);
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$finish;
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end
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a = 'b0;
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b = 'bz;
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#1 if (net !== 1'b0) begin
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$display("FAILED -- a=%b, b=%b, net=%b", a, b, net);
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$finish;
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end
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a = 'b1;
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b = 'b1;
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#1 if (net !== 1'b1) begin
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$display("FAILED -- a=%b, b=%b, net=%b", a, b, net);
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$finish;
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end
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a = 'b1;
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b = 'bx;
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#1 if (net !== 1'bx) begin
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$display("FAILED -- a=%b, b=%b, net=%b", a, b, net);
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$finish;
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end
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a = 'b1;
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b = 'bz;
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#1 if (net !== 1'b1) begin
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$display("FAILED -- a=%b, b=%b, net=%b", a, b, net);
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$finish;
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end
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a = 'bx;
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b = 'bx;
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#1 if (net !== 1'bx) begin
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$display("FAILED -- a=%b, b=%b, net=%b", a, b, net);
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$finish;
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end
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a = 'bx;
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b = 'bz;
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#1 if (net !== 1'bx) begin
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$display("FAILED -- a=%b, b=%b, net=%b", a, b, net);
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$finish;
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end
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a = 'bz;
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b = 'bz;
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#1 if (net !== 1'bz) begin
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$display("FAILED -- a=%b, b=%b, net=%b", a, b, net);
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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