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https://github.com/steveicarus/iverilog.git
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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
29 lines
622 B
Verilog
29 lines
622 B
Verilog
module test14;
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import work14_pkg::*;
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bit clk = 0;
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parameter longint maxvalue = 2**29 + 17;
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logic [29:0] mvalue;
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logic [29:0] lvalue;
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initial begin : clkgen forever #10 clk = ~clk; end
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assign lvalue = maxvalue;
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work14_comp #(.max_out_val(maxvalue)) duv (.clk_i(clk), .val(mvalue));
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initial begin
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@(posedge clk);
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#1;
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if (lvalue !== mvalue) $display ("ERROR due to mismatch between lvalue=%d and mvalue=%d", lvalue, mvalue);
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@(posedge clk);
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#1;
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if (lvalue !== mvalue) $display ("ERROR due to mismatch between lvalue=%d and mvalue=%d", lvalue, mvalue);
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#5;
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$display ("PASSED");
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$finish;
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end
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endmodule
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