mirror of
https://github.com/steveicarus/iverilog.git
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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
86 lines
2.6 KiB
Verilog
86 lines
2.6 KiB
Verilog
/***************************************************************
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** Author: Oswaldo Cadenas ([email protected])
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** Date: September 26 2011
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**
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** Test: Intended to test parametric counter in timebase.vhd
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** the counter has parameters: N for counter length and
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VALUE to flag when the count reaches this value
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**
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** Four counter instances are created here:
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** duv1 with counter default parameters for N and VALUE
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** duv2 with N1, V1 for parameter N, VALUE respectively
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** duv3 with N2, V2 for parameters N, VALUE respectively
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** duv4 with N2 replacing N and VALUE left as default
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**
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** The test for a long time making sure each of the four counter flags TICK become one
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**************************************************************************************/
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module test;
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parameter integer T = 25;
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parameter integer N1 = 8;
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parameter integer N2 = 17;
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parameter integer V1 = 200;
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parameter integer V2 = 17'h16C8A;
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bit clk = 0, reset = 0;
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wire [11:0] count1;
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wire [N1-1:0] count2;
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wire [N2-1:0] count3;
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wire [N2-1:0] count4;
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wire tick1, tick2, tick3, tick4;
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reg tick1_reg, tick2_reg, tick3_reg, tick4_reg;
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initial forever #(T) clk = !clk;
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initial begin
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@(negedge clk);
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reset = 1'b1;
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repeat(6) @(negedge clk);
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reset = 1'b0;
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end
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// duv1 switch
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always @(posedge clk, posedge reset)
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if (reset) tick1_reg <= 1'b0;
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else if (tick1) tick1_reg <= 1'b1;
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// duv2 switch
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always @(posedge clk, posedge reset)
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if (reset) tick2_reg <= 1'b0;
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else if (tick2) tick2_reg <= 1'b1;
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// duv3 switch
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always @(posedge clk, posedge reset)
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if (reset) tick3_reg <= 1'b0;
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else if (tick3) tick3_reg <= 1'b1;
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// duv4 switch
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always @(posedge clk, posedge reset)
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if (reset) tick4_reg <= 1'b0;
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else if (tick4) tick4_reg <= 1'b1;
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initial begin
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#(V2*2*T + 1000);
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if (tick1_reg != 1 || tick2_reg != 1 || tick3_reg != 1 || tick4_reg != 1) begin
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$display ("Counting FAILED");
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$finish;
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end
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else begin
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$display ("PASSED");
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#20;
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$finish;
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end
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end
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timebase duv1 (.clock(clk), .reset(reset), .enable(1'b1), .tick(tick1), .count_value(count1) ); // default parameters
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timebase #(.n(N1), .value(V1))
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duv2 (.clock(clk), .reset(reset), .enable(1'b1), .tick(tick2), .count_value(count2) ); // N1, V1 parameters
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timebase #(N2, V2)
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duv3 (.clock(clk), .reset(reset), .enable(1'b1), .tick(tick3), .count_value(count3) ); // N2, V2 parameters
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timebase #(.n(N2))
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duv4 (.clock(clk), .reset(reset), .enable(1'b1), .tick(tick4), .count_value(count4) ); // only one parameter modified
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endmodule
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