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https://github.com/steveicarus/iverilog.git
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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
54 lines
1.2 KiB
Verilog
54 lines
1.2 KiB
Verilog
/***************************************************************
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** Author: Oswaldo Cadenas ([email protected])
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** Date: September 26 2011
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**
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** Test: Intended to test a system composed of some parametric system
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** that has an adder, a register and an incrementer
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** Each module has parameter: N for data length
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**
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** A system is given parameter P and should return P-1, this is run for M test vectors
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**************************************************************************************/
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module test;
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parameter integer T = 25; // for the clock period
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parameter integer P = 1000; // a constant passed to the system under test
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parameter integer M = 200; // number of test vectors
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int i;
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bit clk = 0, reset = 0;
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byte unsigned x;
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wire [10:0] y;
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initial forever #(T) clk = !clk;
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initial begin
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@(negedge clk);
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reset = 1'b1;
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repeat(6) @(negedge clk);
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reset = 1'b0;
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end
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initial begin
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@(posedge reset);
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@(negedge reset);
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for (i = 0; i < M; i=i+1) begin
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x = {$random} % 255;
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@(negedge clk);
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if (y !== P-1) begin
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$display ("ERROR");
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$finish;
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end
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end
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#100;
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$display ("PASSED");
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$finish;
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end
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const_system #(P) duv (.clk(clk), .reset(reset), .x(x), .y(y) );
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endmodule
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