mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-09-03 16:29:25 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
159 lines
3.7 KiB
VHDL
159 lines
3.7 KiB
VHDL
-- This system does nothing useful
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-- It takes input X and this is registered internally
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-- It computes x+1 and x+const independently
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-- The output is computed as (x+const)-(x+1)=const-1
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-- so the higher level modifies C and then C-1 is returned
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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entity Const_system is
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generic (C: in integer := 500);
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port (clk, reset: in std_logic;
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x: in std_logic_vector (7 downto 0);
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y: out std_logic_vector (10 downto 0) );
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end Const_system;
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library ieee;
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use ieee.std_logic_1164.all;
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entity Add is
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generic (n: integer := 8);
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port (a, b: in std_logic_vector (n-1 downto 0);
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sum: out std_logic_vector (n-1 downto 0);
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cin: in std_logic );
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end Add;
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library ieee;
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use ieee.std_logic_1164.all;
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entity Inc is
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generic (n: integer := 8);
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port (a: in std_logic_vector (n-1 downto 0);
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sum: out std_logic_vector (n-1 downto 0)
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);
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end Inc;
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library ieee;
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use ieee.std_logic_1164.all;
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entity Reg_N is
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generic (n: integer := 4);
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port (clk, reset: in std_logic;
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a: in std_logic_vector (n-1 downto 0);
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a_reg: out std_logic_vector (n-1 downto 0) );
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end Reg_N;
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architecture System_rtl of Const_system is
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-- Register component
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component Reg_N is
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generic (n: integer := 4);
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port (clk, reset: in std_logic;
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a: in std_logic_vector (n-1 downto 0);
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a_reg: out std_logic_vector (n-1 downto 0) );
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end component;
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-- incrementer component
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component Inc is
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generic (n: integer := 8);
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port (a: in std_logic_vector (n-1 downto 0);
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sum: out std_logic_vector (n-1 downto 0)
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);
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end component;
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-- adder component
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component Add is
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generic (n: integer := 8);
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port (a, b: in std_logic_vector (n-1 downto 0);
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sum: out std_logic_vector (n-1 downto 0);
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cin: in std_logic );
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end component;
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signal x_int: std_logic_vector (7 downto 0);
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signal x_inc: std_logic_vector (7 downto 0);
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signal x_sum: std_logic_vector (10 downto 0);
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signal x_ext: std_logic_vector (10 downto 0);
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signal x_inv: std_logic_vector (10 downto 0);
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signal x_dif: std_logic_vector (10 downto 0);
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signal zero, one: std_logic;
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signal const: std_logic_vector (10 downto 0);
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begin
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const <= conv_std_logic_vector (C, 11);
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-- connstant bit 0, 1
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zero <= '0';
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one <= '1';
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-- registering input X
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RegX: Reg_N generic map (n => 8)
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port map ( clk => clk, reset => reset, a => x, a_reg => x_int);
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-- Incrementing input x_int
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incrementer: Inc generic map (n => 8)
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port map (a => x_int, sum => x_inc); -- x + 1
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-- forming 1's complement of x+1
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x_inv <= "111" & not x_inc;
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x_ext <= "000" & x_int;
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-- adding constant to x_int
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addition: Add generic map (n => 11)
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port map (a => x_ext, b => const, cin => zero, sum => x_sum); -- x + 1000
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-- this should get x+1000-(x+1) = 1000-1 = 999
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subtraction: Add generic map (n => 11)
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port map (a => x_sum, b => x_inv, cin => one, sum => x_dif);
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-- registering output X
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RegY: Reg_N generic map (n => 11)
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port map ( clk => clk, reset => reset, a => x_dif, a_reg => y);
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end System_rtl;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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architecture Add_rtl of Add is
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signal cx: std_logic_vector (n downto 0);
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begin
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cx <= ('0' & a) + ('0' & b) + cin;
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sum <= cx (n-1 downto 0);
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end Add_rtl;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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architecture Inc_rtl of Inc is
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signal cx: std_logic_vector (n downto 0);
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begin
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cx <= ('0' & a) + '1';
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sum <= cx (n-1 downto 0);
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end Inc_rtl;
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library ieee;
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use ieee.std_logic_1164.all;
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architecture Reg_rtl of Reg_N is
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begin
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My_register: process (clk, reset)
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begin
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if (reset = '1') then
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a_reg <= (others => '0');
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elsif (clk'event and clk = '1') then
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a_reg <= a;
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end if;
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end process;
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end Reg_rtl;
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