mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-09-03 03:23:31 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
51 lines
997 B
Verilog
51 lines
997 B
Verilog
module switch_primitives();
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wire a;
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wire b0;
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wire b1;
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wire m0;
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wire m1;
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wire t0;
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wire t1;
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reg in;
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reg en;
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bufif0(b0, a, en);
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bufif1(b1, a, en);
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pmos(m0, a, en);
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nmos(m1, a, en);
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tranif0(t0, a, en);
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tranif1(a, t1, en);
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assign a = in;
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initial begin
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$monitor("%b %b %b %b %b %b %b %b %v %v %v %v %v %v",
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en, a, b0, b1, m0, m1, t0, t1,
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b0, b1, m0, m1, t0, t1);
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#1 $display("------------------");
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#1 en = 1'b0; in = 1'b0;
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#1 en = 1'b0; in = 1'b1;
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#1 en = 1'b0; in = 1'bx;
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#1 en = 1'b0; in = 1'bz;
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#1 $display("------------------");
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#1 en = 1'b1; in = 1'b0;
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#1 en = 1'b1; in = 1'b1;
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#1 en = 1'b1; in = 1'bx;
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#1 en = 1'b1; in = 1'bz;
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#1 $display("------------------");
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#1 en = 1'bx; in = 1'b0;
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#1 en = 1'bx; in = 1'b1;
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#1 en = 1'bx; in = 1'bx;
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#1 en = 1'bx; in = 1'bz;
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#1 $display("------------------");
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#1 en = 1'bz; in = 1'b0;
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#1 en = 1'bz; in = 1'b1;
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#1 en = 1'bz; in = 1'bx;
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#1 en = 1'bz; in = 1'bz;
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end
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endmodule
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