mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-09-02 21:48:38 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
88 lines
1.6 KiB
Verilog
88 lines
1.6 KiB
Verilog
/*
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* This is the most basic test of string variables.
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*/
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module main;
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string foo;
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string bar;
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initial begin
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foo = "foo";
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bar = "bar";
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if (foo != "foo") begin
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$display("FAILED -- foo=%0s (1)", foo);
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$finish;
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end
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if (bar != "bar") begin
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$display("FAILED -- bar=%0s (2)", bar);
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$finish;
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end
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if (foo == bar) begin
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$display("FAILED -- %0s == %0s (3)", foo, bar);
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$finish;
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end
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if (! (foo != bar)) begin
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$display("FAILED -- ! (%0s != %0s) (4)", foo, bar);
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$finish;
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end
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if (bar > foo) begin
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$display("FAILED -- %s > %s (5)", bar, foo);
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$finish;
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end
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if (bar >= foo) begin
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$display("FAILED -- %s >= %s (6)", bar, foo);
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$finish;
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end
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if (foo < bar) begin
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$display("FAILED -- %s < %s (7)", foo, bar);
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$finish;
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end
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if (foo <= bar) begin
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$display("FAILED -- %s <= %s (8)", foo, bar);
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$finish;
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end
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bar = foo;
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if (foo != bar) begin
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$display("FAILED -- %0s != %0s (9)", foo, bar);
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$finish;
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end
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if (foo > bar) begin
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$display("FAILED -- %0s > %0s (10)", foo, bar);
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$finish;
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end
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if (foo < bar) begin
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$display("FAILED -- %0s < %0s (11)", foo, bar);
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$finish;
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end
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if (! (foo == bar)) begin
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$display("FAILED -- ! (%0s == %0s) (12)", foo, bar);
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$finish;
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end
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if (! (foo <= bar)) begin
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$display("FAILED -- ! (%0s <= %0s) (13)", foo, bar);
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$finish;
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end
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if (! (foo >= bar)) begin
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$display("FAILED -- ! (%0s >= %0s) (14)", foo, bar);
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$finish;
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end
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$display("PASSED");
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$finish;
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end
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endmodule // main
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