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Lars-Peter Clausen
7df00d3070
Check that width and sign determination works correctly for package scoped function calls. Signed-off-by: Lars-Peter Clausen <[email protected]>
29 lines
503 B
Verilog
29 lines
503 B
Verilog
// Check that the signedness of package scoped functions is handled correctly,
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// when passing the result of the function to a system function
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package P;
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function shortint s();
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return -1;
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endfunction
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function bit [15:0] u();
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return -1;
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endfunction
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endpackage
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module test;
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string s;
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initial begin
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s = $sformatf("%0d %0d", P::s(), P::u());
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if (s == "-1 65535") begin
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$display("PASSED");
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end else begin
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$display("FAILED s=%s", s);
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end
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end
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endmodule
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