mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-09-03 16:29:25 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
172 lines
3.1 KiB
Verilog
172 lines
3.1 KiB
Verilog
// This tests SystemVerilog interfaces
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012 by Iztok Jeras.
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module test ();
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// error counter
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bit err = 0;
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logic clk = 1'b1;
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logic rst = 1'b1; // reset
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integer rst_cnt = 0;
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// clock generator
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always #5 clk = ~clk;
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// reset is removed after a delay
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always @ (posedge clk)
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begin
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rst_cnt <= rst_cnt + 1;
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rst <= rst_cnt <= 3;
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end
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// counters
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int cnt;
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int cnt_src;
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int cnt_drn;
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// add all counters
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assign cnt = cnt_src + cnt_drn + inf.cnt;
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// finish report
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initial begin
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wait (cnt == 3*16);
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if (!err) $display("PASSED");
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$finish;
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end
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// interface instance
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handshake inf (
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.clk (clk),
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.rst (rst)
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);
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// source instance
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source #(
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.RW (8),
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.RP (8'b11100001)
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) source (
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.clk (clk),
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.rst (rst),
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.inf (inf),
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.cnt (cnt_src)
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);
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// drain instance
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drain #(
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.RW (8),
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.RP (8'b11010100)
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) drain (
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.clk (clk),
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.rst (rst),
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.inf (inf),
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.cnt (cnt_drn)
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);
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endmodule
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// interface definition
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interface handshake #(
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parameter int unsigned WC = 32
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)(
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input logic clk,
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input logic rst
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);
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// modport signals
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logic req; // request
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logic grt; // grant
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logic inc; // increment
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// local signals
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integer cnt; // counter
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// source
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modport src (
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output req,
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input grt
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);
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// drain
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modport drn (
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input req,
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output grt
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);
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// incremet condition
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assign inc = req & grt;
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// local logic (counter)
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always @ (posedge clk, posedge rst)
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if (rst) cnt <= '0;
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else cnt <= cnt + inc;
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endinterface
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// source module
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module source #(
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// random generator parameters
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parameter int unsigned RW=1, // LFSR width
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parameter bit [RW-1:0] RP='0, // LFSR polinom
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parameter bit [RW-1:0] RR='1 // LFSR reset state
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)(
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input logic clk,
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input logic rst,
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handshake.src inf,
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output integer cnt
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);
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// LFSR
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logic [RW-1:0] rnd;
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// LFSR in Galois form
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always @ (posedge clk, posedge rst)
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if (rst) rnd <= RR;
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else rnd <= {rnd[0], rnd[RW-1:1]} ^ ({RW{rnd[0]}} & RP);
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// counter
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always @ (posedge clk, posedge rst)
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if (rst) cnt <= 32'd0;
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else cnt <= cnt + (inf.req & inf.grt);
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// request signal
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assign inf.req = rnd[0];
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endmodule
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// drain module
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module drain #(
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// random generator parameters
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parameter int unsigned RW=1, // LFSR width
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parameter bit [RW-1:0] RP='0, // LFSR polinom
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parameter bit [RW-1:0] RR='1 // LFSR reset state
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)(
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input logic clk,
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input logic rst,
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handshake.drn inf,
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output integer cnt
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);
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// LFSR
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logic [RW-1:0] rnd;
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// LFSR in Galois form
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always @ (posedge clk, posedge rst)
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if (rst) rnd <= RR;
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else rnd <= {rnd[0], rnd[RW-1:1]} ^ ({RW{rnd[0]}} & RP);
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// counter
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always @ (posedge clk, posedge rst)
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if (rst) cnt <= 32'd0;
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else cnt <= cnt + (inf.req & inf.grt);
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// grant signal
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assign inf.grt = rnd[0];
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endmodule
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