mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-09-03 06:03:11 +02:00
Check that the signedness of the return value of methods is handled correctly. * When sign extending * When passing as a value to a system function Check this for both methods on user defined class as well as built-in methods on SystemVerilog types. Signed-off-by: Lars-Peter Clausen <[email protected]>
31 lines
520 B
Verilog
31 lines
520 B
Verilog
// Check that the signedness of methods on user defined classes is handled
|
|
// correctly when passing the result to a system function.
|
|
|
|
module test;
|
|
|
|
class C;
|
|
function shortint s;
|
|
return -1;
|
|
endfunction
|
|
|
|
function bit [15:0] u;
|
|
return -1;
|
|
endfunction
|
|
endclass
|
|
|
|
C c;
|
|
string s;
|
|
|
|
initial begin
|
|
c = new;
|
|
|
|
s = $sformatf("%0d %0d", c.s(), c.u());
|
|
if (s == "-1 65535") begin
|
|
$display("PASSED");
|
|
end else begin
|
|
$display("FAILED s=%s", s);
|
|
end
|
|
end
|
|
|
|
endmodule
|