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Check that string literals can be assigned to byte arrays. Check that invalid target array types are reported as errors. Signed-off-by: Lars-Peter Clausen <[email protected]>
18 lines
254 B
Verilog
18 lines
254 B
Verilog
// Check that string literals cannot be connected to output byte array ports.
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module M (
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output byte out [0:1]
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);
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initial begin
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out = "CD";
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end
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endmodule
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module test;
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M i_m("AB"); // Error: output expression is not assignable
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endmodule
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