Files
iverilog/ivtest/ivltests/sv_byte_array_string_fail3.v
T
Lars-Peter Clausen 6ffb4b9a3a Add regression tests for string literals assigned to byte arrays
Check that string literals can be assigned to byte arrays. Check that
invalid target array types are reported as errors.

Signed-off-by: Lars-Peter Clausen <[email protected]>
2026-05-06 19:20:47 -07:00

18 lines
254 B
Verilog

// Check that string literals cannot be connected to output byte array ports.
module M (
output byte out [0:1]
);
initial begin
out = "CD";
end
endmodule
module test;
M i_m("AB"); // Error: output expression is not assignable
endmodule