mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-09-02 22:38:49 +02:00
Lars-Peter Clausen
6ffb4b9a3a
Check that string literals can be assigned to byte arrays. Check that invalid target array types are reported as errors. Signed-off-by: Lars-Peter Clausen <[email protected]>
9 lines
184 B
Verilog
9 lines
184 B
Verilog
// Check that string literals cannot be assigned directly to multi-dimensional
|
|
// byte arrays.
|
|
|
|
module test;
|
|
|
|
byte value [0:1][0:3] = "AB"; // Error: string is not nested
|
|
|
|
endmodule
|