mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-09-03 16:29:25 +02:00
Lars-Peter Clausen
74491cfe9f
Check that continuous assignment of an assignment pattern to a single element unpacked array is accepted. Check that assigning a scalar expression to the whole unpacked array is rejected for both procedural and continuous assignments. Check that a selected element of a single element static unpacked array can be used in a continuous l-value concatenation. Signed-off-by: Lars-Peter Clausen <[email protected]>
11 lines
169 B
Verilog
11 lines
169 B
Verilog
// Check that scalar expressions can not be continuously assigned to single
|
|
// element unpacked arrays.
|
|
|
|
module test;
|
|
|
|
wire [31:0] a[0:0];
|
|
|
|
assign a = 1;
|
|
|
|
endmodule
|