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iverilog/ivtest/ivltests/sv_array_cassign_single.v
T
Lars-Peter Clausen 74491cfe9f Add regression tests for single element unpacked array assignments
Check that continuous assignment of an assignment pattern to a single element
unpacked array is accepted. Check that assigning a scalar expression to the
whole unpacked array is rejected for both procedural and continuous
assignments.

Check that a selected element of a single element static unpacked array can be
used in a continuous l-value concatenation.

Signed-off-by: Lars-Peter Clausen <[email protected]>
2026-05-16 21:11:30 -07:00

31 lines
543 B
Verilog

// Check that continuous array assignment to single element unpacked arrays is
// supported.
module test;
reg failed;
wire [31:0] a[0:0];
reg [31:0] b[0:0];
assign a = b;
`define check(val, exp) \
if (val !== exp) begin \
$display("FAILED(%0d). '%s' expected %0d, got %0d", `__LINE__, \
`"val`", exp, val); \
failed = 1'b1; \
end
initial begin
failed = 1'b0;
b[0] = 32'd42;
#1;
`check(a[0], 32'd42);
if (!failed) begin
$display("PASSED");
end
end
endmodule