mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-09-03 03:23:31 +02:00
Lars-Peter Clausen
4ef5b02bcd
Check various different scenarios for array compatibility in continuous array assign. Both testing cases that should work and cases that should fail. Signed-off-by: Lars-Peter Clausen <[email protected]>
15 lines
224 B
Verilog
15 lines
224 B
Verilog
// Check that it is an error trying to continuously assign a scalar expression
|
|
// to a unpacked array.
|
|
|
|
module test;
|
|
|
|
wire [1:0] x[1:0];
|
|
|
|
assign x = 1'b1 + 1'b1;
|
|
|
|
initial begin
|
|
$display("FAILED");
|
|
end
|
|
|
|
endmodule
|