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Lars-Peter Clausen
b7ef0b5d88
Check that continuous assignments to both signed and unsigned 2-state arrays are supported. Signed-off-by: Lars-Peter Clausen <[email protected]>
31 lines
536 B
Verilog
31 lines
536 B
Verilog
// Check that continuous assignments to 2-state arrays are supported.
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module test;
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bit failed = 1'b0;
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`define check(expr, val) do \
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if (expr !== val) begin \
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$display("FAILED(%0d): `%s`, expected %0d, got %0d", `__LINE__, `"expr`", val, expr); \
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failed = 1'b1; \
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end \
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while (0)
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int a1[0:1];
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bit [31:0] a2[0:1];
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assign a1[0] = -10;
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assign a2[0] = 20;
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initial begin
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#0
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`check(a1[0], -10);
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`check(a2[0], 20);
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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