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Lars-Peter Clausen
e1691c48fe
Check that assigning array that have opposite left-to-righto order for their dimensions have their elements assigned in reversed order. Signed-off-by: Lars-Peter Clausen <[email protected]>
38 lines
658 B
Verilog
38 lines
658 B
Verilog
// Check that continuous array assignment for multi-dimensional arrays behaves
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// correctly when left-to-right order is reversed.
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module test;
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logic [31:0] x[2:0][6:0][4:0];
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wire [31:0] y[0:2][6:0][0:4];
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assign y = x;
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initial begin
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static integer idx = 1;
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static bit failed = 1'b0;
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foreach (x[i,j,k]) begin
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x[i][j][k] = idx;
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idx++;
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end
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#1
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idx = 1;
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foreach (y[i,j,k]) begin
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$display(i, j, k, y[i][j][k]);
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if (y[i][j][k] !== idx) begin
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$display("FAILED");
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failed = 1'b1;
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end
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idx++;
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end
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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