Files
iverilog/ivtest/ivltests/sv_array_cassign1.v
T
Lars-Peter Clausen 4ef5b02bcd Add regression tests for continuous array assign compatibility
Check various different scenarios for array compatibility in continuous
array assign. Both testing cases that should work and cases that should
fail.

Signed-off-by: Lars-Peter Clausen <[email protected]>
2022-12-17 15:47:18 -08:00

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Verilog

// Check that continuous assignment of two compatible arrays is supported
module test;
wire [1:0] x[1:0];
wire [1:0] y[1:0];
assign x = y;
initial begin
$display("PASSED");
end
endmodule