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The test checks that all invalid declarations produce an error and also do not crash the application. Signed-off-by: Lars-Peter Clausen <[email protected]>
16 lines
313 B
Verilog
16 lines
313 B
Verilog
// Check that structs with invalid member declarations are deteceted, report an
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// error and do not cause a crash
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module test;
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struct packed {
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logic x; // OK
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logic y, z; // OK
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logic bit; // Invalid
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logic a b c; // Invalid
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logc d; // Invalid
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e; // Invalid
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} s;
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endmodule
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