mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-09-03 01:13:47 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
39 lines
813 B
Verilog
39 lines
813 B
Verilog
module main;
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typedef struct packed {
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logic [7:0] high;
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logic [7:0] low;
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} word_t;
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// Declare word1 as a VARIABLE
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word_t word1;
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// Declare word2 as a VARIABLE
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word_t word2;
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always @(word1) begin
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word2.high = word1.high;
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word2.low = word1.low;
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end
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initial begin
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word1 = 16'haa_55;
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if (word1.high !== 8'haa || word1.low !== 8'h55) begin
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$display("FAILED: word1 = %h, word1.high = %h, word1.low = %h",
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word1, word1.high, word1.low);
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$finish;
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end
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#1 /* Make sure word2 assign propagates */;
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if (word2.high !== 8'haa || word2.low !== 8'h55) begin
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$display("FAILED: word2 = %h, word2.high = %h, word2.low = %h",
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word1, word2.high, word2.low);
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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