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By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
87 lines
1.8 KiB
Verilog
87 lines
1.8 KiB
Verilog
`timescale 100 ps / 10 ps
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module test;
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reg cdn, cp, d;
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wire qr, qp;
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initial begin
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$timeformat(-9, 2, " ns", 9);
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$monitor("%t - cdn=%b, cp=%b, d=%b, qr=%b, qp=%b",$time,cdn,cp,d,qr,qp);
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// Reset the FF.
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cp = 0; d = 1;
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#100 cdn = 0;
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#100 cdn = 1;
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// Toggle in some data.
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#100 cp = 1;
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#100 cp = 0; d = 0;
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#100 cp = 1;
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#100 cp = 0; d = 1;
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#100 cp = 1;
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end
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dff_rtl dutr(qr, d, cp, cdn); // This one works fine.
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dff_prm dutp(qp, d, cp, cdn); // This one has no delay.
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endmodule
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// The RTL version appears to work fine.
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module dff_rtl (q, d, cp, cdn);
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output q;
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input d;
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input cp;
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input cdn;
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reg qi;
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always @(posedge cp or negedge cdn) begin
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if (~cdn) qi <= 1'b0;
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else qi <= d;
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end
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buf (q, qi);
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specify
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specparam tpd_cp_q_lh = 6;
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specparam tpd_cp_q_hl = 7;
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specparam tpd_cdn_q_lh = 0;
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specparam tpd_cdn_q_hl = 3;
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if (cdn) (posedge cp => (q +: d)) = (tpd_cp_q_lh, tpd_cp_q_hl);
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(negedge cdn => (q +: 1'b0)) = (tpd_cdn_q_lh, tpd_cdn_q_hl);
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endspecify
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endmodule
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// The primitive version has no delay.
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module dff_prm (q, d, cp, cdn);
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output q;
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input d, cp, cdn;
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UDP_DFF G3(q, d, cp, cdn);
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specify
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specparam tpd_cp_q_lh = 6;
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specparam tpd_cp_q_hl = 7;
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specparam tpd_cdn_q_lh = 0;
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specparam tpd_cdn_q_hl = 3;
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if (cdn) (posedge cp => (q +: d)) = (tpd_cp_q_lh, tpd_cp_q_hl);
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(negedge cdn => (q +: 1'b0)) = (tpd_cdn_q_lh, tpd_cdn_q_hl);
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endspecify
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endmodule
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// This is overly simplistic, but it works for this example.
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primitive UDP_DFF(q, d, cp, cdn);
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output q;
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reg q;
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input d, cp, cdn;
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table
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// d cp cdn q0 q
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* ? ? : ? : - ;
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? n ? : ? : - ;
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0 r 1 : ? : 0 ;
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1 r 1 : ? : 1 ;
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? ? 0 : ? : 0 ;
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? ? p : ? : - ;
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endtable
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endprimitive
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