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https://github.com/steveicarus/iverilog.git
synced 2026-09-03 08:25:32 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
35 lines
617 B
Verilog
35 lines
617 B
Verilog
module main;
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longint foo, bar = 10;
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longint wire_res;
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longint var_res;
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assign wire_res = foo*bar;
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initial begin
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foo = 9;
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var_res = foo * bar;
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$display("%0d * %0d = %0d %0d", foo, bar, foo * bar, var_res);
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if ((foo * bar) !== 90) begin
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$display("FAILED");
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$finish;
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end
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if (var_res !== 90) begin
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$display("FAILED");
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$finish;
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end
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#0; // allow CA to propagate
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$display("%0d * %0d = %0d", foo, bar, wire_res);
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if (wire_res !== 90) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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