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https://github.com/steveicarus/iverilog.git
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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
46 lines
1.0 KiB
Verilog
46 lines
1.0 KiB
Verilog
module top;
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parameter seeq1 = 6'sb111000 === 4'sb1000;
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parameter seeqx = 6'sbxxx000 === 4'sbx000;
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parameter seeqz = 6'sbzzz000 === 4'sbz000;
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parameter seq1 = 6'sb111000 == 4'sb1000;
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parameter seqx = 6'sbxxx000 == 4'sbx000;
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parameter seqz = 6'sbzzz000 == 4'sbz000;
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reg pass;
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initial begin
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pass = 1'b1;
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if (seeq1 !== 1'b1) begin
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$display("FAILED: signed === (1), got %b", seeq1);
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pass = 1'b0;
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end
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if (seeqx !== 1'b1) begin
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$display("FAILED: signed === (x), got %b", seeqx);
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pass = 1'b0;
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end
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if (seeqz !== 1'b1) begin
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$display("FAILED: signed === (z), got %b", seeqz);
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pass = 1'b0;
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end
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if (seq1 !== 1'b1) begin
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$display("FAILED: signed == (1), got %b", seq1);
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pass = 1'b0;
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end
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if (seqx !== 1'bx) begin
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$display("FAILED: signed == (x), got %b", seqx);
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pass = 1'b0;
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end
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if (seqz !== 1'bx) begin
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$display("FAILED: signed == (z), got %b", seqz);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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