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https://github.com/steveicarus/iverilog.git
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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
23 lines
496 B
Verilog
23 lines
496 B
Verilog
`begin_keywords "1364-2005"
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module top;
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reg pass;
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reg [3:0] var;
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integer lp;
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initial begin
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pass = 1'b1;
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for (lp = 0; lp < 16; lp = lp + 1) begin
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var = lp;
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// This should bit extend var as unsigned and then
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// convert it into a signed value.
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if (lp !== $signed(var+5'b0)) begin
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$display("FAILED: expected %2d, got %2d", lp, $signed(var+5'b0));
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pass = 1'b0;
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end
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end
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if (pass) $display("PASSED");
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end
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endmodule
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`end_keywords
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