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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
11 lines
207 B
Verilog
11 lines
207 B
Verilog
module top;
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// Does this have to be signed?
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wire signed [7:0] out;
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// Either of these will not expand correctly.
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// assign out = 'sh1f;
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assign out = 5'sh1f;
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initial #1 $displayb(out);
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endmodule
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