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https://github.com/steveicarus/iverilog.git
synced 2026-09-03 03:23:31 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
46 lines
1.2 KiB
Verilog
46 lines
1.2 KiB
Verilog
module main;
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reg signed [7:0] a;
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reg [7:0] b;
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initial begin
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// Make sure the arithmetic right shift sign extends
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$display("simple arithmetic right shift");
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a = 8'b11001001;
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$display("before: a = %b", a);
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a = a>>>1;
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$display("after: a = %b", a);
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if (a !== 8'b11100100) begin
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$display("FAILED");
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$finish;
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end
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// The concatenation operator is always unsigned, so
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// it must turn off sign extension.
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$display("concatenated arithmetic right shift");
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a = 8'b11001001;
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b = 0;
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$display("before: a = %b", a);
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{a,b} = {a,b}>>>1;
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$display("after: a = %b", a);
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if (a !== 8'b01100100) begin
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$display("FAILED");
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$finish;
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end
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// The concatenation operator is always unsigned, but
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// we can turn on signed behavior with $signed.
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$display("concatenated arithmetic right shift with $signed");
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a = 8'b11001001;
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b = 0;
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$display("before: a = %b", a);
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{a,b} = $signed({a,b})>>>1;
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$display("after: a = %b", a);
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if (a !== 8'b11100100) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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