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https://github.com/steveicarus/iverilog.git
synced 2026-09-02 21:48:38 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
30 lines
648 B
Verilog
30 lines
648 B
Verilog
module main;
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reg [7:0] xu;
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reg signed [7:0] xs;
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initial begin
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xu = 8'b1100_0000;
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xs = 8'b1100_0000;
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xu = xs >>> 3;
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xs = xu >>> 3;
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// IEEE1364-2005 Secion 5.5.1 Rules for Expression Types
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// "Expression type depends only on the operands. It does not depend
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// on the left-hand side (if any)."
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if (xu !== 8'b1111_1000) begin
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$display("FAILED -- xu = xs >>> 3 failed. xu=%b", xu);
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$finish;
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end
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if (xs !== 8'b0001_1111) begin
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$display("FAILED -- xs = xu >>> 3 failed. xs=%b", xs);
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$finish;
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end
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$display("PASSED");
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end // initial begin
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endmodule // main
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