mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-09-03 08:25:32 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
108 lines
3.0 KiB
Verilog
108 lines
3.0 KiB
Verilog
/*
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* Copyright (c) 2000 Mark Schellhorn <[email protected]>
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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/****************************************************************************
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The following code illustrates an apparent bug in the VCS v5.2 simulator.
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The check for whether or not the memory[0] array element was set correctly
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fails; yet the $display statement immediately after the check shows the
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memory[0] element actually has been set correctly.
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I've noted that if the $display and the check are reversed, the $display
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is incorrect but the check passes.
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This appears to be a problem with the simulator's internal scheduler.
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***************************************************************************/
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module bug_test;
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reg [1:0] temp;
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initial begin
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/********** First test. */
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$display("Running first test.\n");
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// Try setting memory array in other module using hierarchical
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// references & concatenation.
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temp = 2'h3;
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top.memory.memory[0] = {2'h0,temp};
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top.memory.memory[0] = {top.memory.memory[0],temp};
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// Check that setting was made correctly
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if (top.memory.memory[0] != {2{temp}}) begin
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$display("ERROR! top.memory.memory[0] failed to get");
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$display("set correctly!");
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end else begin
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$display("PASS! top.memory.memory[0] set correctly.");
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end
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// Display the value that was checked
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$display("top.memory.memory[0] = %h",top.memory.memory[0]);
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/********** Second test. */
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$display("\nRunning second test.\n");
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// Try setting memory array in other module using hierarchical
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// references & concatenation.
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temp = 2'h3;
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top.memory.memory[1] = {2'h0,temp};
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top.memory.memory[1] = {top.memory.memory[1],temp};
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// Display the value that will be checked
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$display("top.memory.memory[1] = %h",top.memory.memory[1]);
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// Check that setting was made correctly
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if (top.memory.memory[1] != {2{temp}}) begin
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$display("ERROR! top.memory.memory[1] failed to get");
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$display("set correctly!");
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end else begin
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$display("PASS! top.memory.memory[1] set correctly.");
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end
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// Display the value that was checked
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$display("top.memory.memory[1] = %h",top.memory.memory[1]);
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$finish(0);
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end
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endmodule
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// Module containing a memory array
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module memory;
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reg [3:0] memory [0:1];
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endmodule
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// Module to instantiate test and memory modules
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module top;
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bug_test bug_test();
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memory memory();
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endmodule
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