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https://github.com/steveicarus/iverilog.git
synced 2026-09-03 16:29:25 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
24 lines
426 B
Verilog
24 lines
426 B
Verilog
/*
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* part select in continuous assignment.
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*/
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`timescale 1ns/1ns
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module main;
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reg [3:0] src;
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wire foo = src[3:1] == 3'b101;
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integer idx;
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initial
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begin
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for (idx = 0 ; idx < 16 ; idx = idx+1) begin
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src = idx;
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#1 if (foo !== (src[3:1] == 3'b101)) begin
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$display("FAILED -- src=%b, foo=%b", src, foo);
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$finish;
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end
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end
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$display("PASSED");
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end // initial begin
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endmodule
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