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https://github.com/steveicarus/iverilog.git
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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
29 lines
818 B
Verilog
29 lines
818 B
Verilog
module top;
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integer res, idx;
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wire [24*8-1:0] wval;
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wire [24*8-1:0] warr [0:1];
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reg [24*8-1:0] rval;
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initial begin
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idx = 0;
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// res = $sscanf(); // A function must have at least one argument!
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res = $sscanf("A string");
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res = $sscanf(wval);
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res = $sscanf("A string", wval);
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res = $sscanf("A string", "%s", top);
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res = $sscanf("A string", "%s", wval);
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res = $sscanf("A string", "%s %s", rval, warr[0]);
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// This is an invalid fd, but it passes the compiletf routine checks.
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// It would get caught by the run time if the compiletf routines did
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// not fail.
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res = $fscanf(1);
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res = $fscanf("A string");
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res = $fscanf(1, wval);
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res = $fscanf(1, "%s", top);
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res = $fscanf(1, "%s", wval);
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res = $fscanf(1, "%s %s", rval, warr[0]);
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end
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endmodule
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