mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-09-07 11:51:38 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
92 lines
2.2 KiB
Verilog
92 lines
2.2 KiB
Verilog
module top;
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parameter real rpar = 2.0;
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real rvar;
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real rarr [1:0];
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real rout, rtmp;
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wire real wrarr [1:0];
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wire real wrbslv, wrpslv, wruplv, wrdolv;
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wire real wrbstr, wrpstr, wruptr, wrdotr;
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wire real wrpbs = rpar[0];
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wire real wrpps = rpar[0:0];
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wire real wrpup = rpar[0+:1];
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wire real wrpdo = rpar[0-:1];
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wire real wrbs = rvar[0];
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wire real wrps = rvar[0:0];
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wire real wrup = rvar[0+:1];
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wire real wrdo = rvar[0-:1];
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wire real wrabs = rarr[0][0];
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wire real wraps = rarr[0][0:0];
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wire real wraup = rarr[0][0+:1];
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wire real wrado = rarr[0][0-:1];
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assign wrbslv[0] = rvar;
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assign wrpslv[0:0] = rvar;
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assign wruplv[0+:1] = rvar;
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assign wrdolv[0-:1] = rvar;
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assign wrarr[0][0] = rvar;
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assign wrarr[0][0:0] = rvar;
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assign wrarr[0][0+:1] = rvar;
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assign wrarr[0][0-:1] = rvar;
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tran(wrbstr[0], wrarr[1]);
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tran(wrpstr[0:0], wrarr[1]);
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tran(wruptr[0+:1], wrarr[1]);
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tran(wrdotr[0-:1], wrarr[1]);
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submod1 s1 (wrbstr[0], wrpstr[0:0], wruptr[0+:1], wrdotr[0-:1]);
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submod2 s2 (wrbstr[0], wrpstr[0:0], wruptr[0+:1], wrdotr[0-:1]);
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submod3 s3 (wrbstr[0], wrpstr[0:0], wruptr[0+:1], wrdotr[0-:1]);
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initial begin
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rtmp = rpar[0];
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rtmp = rpar[0:0];
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rtmp = rpar[0+:1];
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rtmp = rpar[0-:1];
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rtmp = rvar[0];
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rtmp = rvar[0:0];
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rtmp = rvar[0+:1];
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rtmp = rvar[0-:1];
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rtmp = rarr[0][0];
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rtmp = rarr[0][0:0];
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rtmp = rarr[0][0+:1];
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rtmp = rarr[0][0-:1];
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rout[0] = 2.0;
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rout[0:0] = 2.0;
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rout[0+:1] = 2.0;
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rout[0-:1] = 2.0;
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rarr[0][0] = 1.0;
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rarr[0][0:0] = 1.0;
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rarr[0][0+:1] = 1.0;
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rarr[0][0-:1] = 1.0;
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end
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endmodule
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module submod1(arg1, arg2, arg3, arg4);
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input arg1, arg2, arg3, arg4;
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wire real arg1, arg2, arg3, arg4;
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initial $display("In submod1 with %g, %g, %g, %g", arg1, arg2, arg3, arg4);
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endmodule
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module submod2(arg1, arg2, arg3, arg4);
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output arg1, arg2, arg3, arg4;
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real arg1, arg2, arg3, arg4;
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initial $display("In submod2 with %g, %g, %g, %g", arg1, arg2, arg3, arg4);
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endmodule
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module submod3(arg1, arg2, arg3, arg4);
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inout arg1, arg2, arg3, arg4;
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wire real arg1, arg2, arg3, arg4;
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initial $display("In submod3 with %g, %g, %g, %g", arg1, arg2, arg3, arg4);
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endmodule
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