mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-09-07 11:51:38 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
256 lines
5.5 KiB
Verilog
256 lines
5.5 KiB
Verilog
`timescale 1ns/1ps
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primitive not_u (out, in);
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output out;
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input in;
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table
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0 : 1;
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1 : 0;
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endtable
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endprimitive
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// Any instance of this gate will use the small time scale that was
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// in place when it was defined.
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module gate_sdf(out, in);
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output out;
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input in;
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wire out, in;
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assign out = ~in;
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specify
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(in => out) = (0.5, 0.5);
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endspecify
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endmodule
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/*
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* Icarus does not currently support UDPs with a variable delay.
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* It also needs to support NULL decay delays, buf/not/etc. should
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* only allow two delays maximum.
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*/
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module top;
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initial begin
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$monitor("%.3f", $realtime,, sml_const.test, sml_var.test,
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sml_const.out_g, sml_const.out_u,
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sml_const.out_m, sml_const.out_s,
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sml_var.out_g, sml_var.out_u,,
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sml_const.out_f, med_const.out_f,
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lrg_const.out_f,,
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med_const.test, med_var.test,
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med_const.out_g, med_const.out_u,
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med_const.out_m, med_const.out_s,
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med_var.out_g, med_var.out_u,,
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lrg_const.test, lrg_var.test,
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lrg_const.out_g, lrg_const.out_u,
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lrg_const.out_m, lrg_const.out_s,
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lrg_var.out_g, lrg_var.out_u);
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#1.3 $finish(0);
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end
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endmodule
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/*
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* These should have a positive edge at 1234 time ticks.
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*/
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// Check that constant delays are scaled correctly.
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module sml_const;
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reg test, in;
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wire out_g, out_u, out_m, out_s, out_f;
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not #(1.134, 0) dut_g (out_g, in);
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not_u #(1.134, 0) dut_u (out_u, in);
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sml_inv dut_m (out_m, in);
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gate_sdf dut_f (out_f, in);
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sml_sdf dut_s (out_s, in);
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initial begin
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$sdf_annotate("ivltests/real_delay.sdf");
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$sdf_annotate("ivltests/real_delay_sml.sdf");
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in = 1'b1;
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in <= #0.1 1'b0;
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test = 1'b0;
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#1.234 test = 1'b1;
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end
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endmodule
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// Check that the specify delays are scaled correctly.
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module sml_inv(out, in);
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output out;
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input in;
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wire out, in;
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assign out = ~in;
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specify
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(in => out) = (1.134, 0);
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endspecify
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endmodule
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// Check that the SDF delays scale correctly.
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module sml_sdf(out, in);
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output out;
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input in;
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wire out, in;
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assign out = ~in;
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specify
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(in => out) = (0.5, 0.5);
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endspecify
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endmodule
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// Check that variable delays are scaled correctly.
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module sml_var;
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reg test, in;
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real dly, dly2, dly3;
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wire out_g, out_u;
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not #(dly2, dly3) dut_g (out_g, in);
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not_u #(dly2, dly3) dut_u (out_u, in);
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initial begin
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in = 1'b1;
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in <= #0.1 1'b0;
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dly = 1.234;
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dly2 = 1.134;
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dly3 = 0.0;
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test = 1'b0;
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#(dly) test = 1'b1;
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end
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endmodule
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`timescale 1ns/10ps
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/*
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* These should have a positive edge at 1230 time ticks.
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*/
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// Check that constant delays are scaled correctly.
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module med_const;
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reg test, in;
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wire out_g, out_u, out_m, out_s, out_f;
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not #(1.134, 0) dut_g (out_g, in);
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not_u #(1.134, 0) dut_u (out_u, in);
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med_inv dut_m (out_m, in);
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gate_sdf dut_f (out_f, in);
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med_sdf dut_s (out_s, in);
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initial begin
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$sdf_annotate("ivltests/real_delay.sdf");
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$sdf_annotate("ivltests/real_delay_med.sdf");
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in = 1'b1;
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in <= #0.1 1'b0;
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test = 1'b0;
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#1.234 test = 1'b1;
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end
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endmodule
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// Check that the specify delays are scaled correctly.
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module med_inv(out, in);
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output out;
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input in;
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wire out, in;
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assign out = ~in;
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specify
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(in => out) = (1.134, 0);
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endspecify
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endmodule
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// Check that the SDF delays scale correctly.
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module med_sdf(out, in);
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output out;
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input in;
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wire out, in;
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assign out = ~in;
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specify
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(in => out) = (0.5, 0.5);
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endspecify
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endmodule
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// Check that variable delays are scaled correctly.
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module med_var;
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reg test, in;
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real dly, dly2, dly3;
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wire out_g, out_u;
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not #(dly2, dly3) dut_g (out_g, in);
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not_u #(dly2, dly3) dut_u (out_u, in);
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initial begin
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in = 1'b1;
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in <= #0.1 1'b0;
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dly = 1.234;
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dly2 = 1.134;
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dly3 = 0.0;
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test = 1'b0;
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#(dly) test = 1'b1;
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end
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endmodule
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`timescale 1ns/100ps
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/*
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* These should have a positive edge at 1200 time ticks.
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*/
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// Check that constant delays are scaled correctly.
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module lrg_const;
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reg test, in;
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wire out_g, out_u, out_m, out_s, out_f;
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not #(1.134, 0) gate (out_g, in);
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not_u #(1.134, 0) dut_u (out_u, in);
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lrg_inv dut_m (out_m, in);
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gate_sdf dut_f (out_f, in);
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lrg_sdf dut_s (out_s, in);
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initial begin
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$sdf_annotate("ivltests/real_delay.sdf");
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$sdf_annotate("ivltests/real_delay_lrg.sdf");
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in = 1'b1;
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in <= #0.1 1'b0;
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test = 1'b0;
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#1.234 test = 1'b1;
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end
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endmodule
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// Check that the specify delays are scaled correctly.
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module lrg_inv(out, in);
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output out;
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input in;
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wire out, in;
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assign out = ~in;
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specify
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(in => out) = (1.134, 0);
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endspecify
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endmodule
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// Check that the SDF delays scale correctly.
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module lrg_sdf(out, in);
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output out;
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input in;
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wire out, in;
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assign out = ~in;
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specify
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(in => out) = (0.5, 0.5);
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endspecify
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endmodule
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// Check that variable delays are scaled correctly.
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module lrg_var;
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reg test, in;
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real dly, dly2, dly3;
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wire out_g, out_u;
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not #(dly2, dly3) dut_g (out_g, in);
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not_u #(dly2, dly3) dut_u (out_u, in);
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initial begin
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in = 1'b1;
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in <= #0.1 1'b0;
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dly = 1.234;
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dly2 = 1.134;
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dly3 = 0.0;
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test = 1'b0;
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#(dly) test = 1'b1;
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end
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endmodule
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