mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-09-03 06:03:11 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
44 lines
909 B
Verilog
44 lines
909 B
Verilog
/*
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* 23.2.2.3 Rules for determining port kind, data type, and direction says
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*
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* For output ports, the default port kind depends on how the data type is
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* specified:
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* - If the data type is omitted or declared with the implicit_data_type
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* syntax, the port kind shall default to a net of default net type.
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* - If the data type is declared with the explicit data_type syntax, the port
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* kind shall default to variable.
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*/
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typedef enum { A, B } E;
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module main;
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E in;
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wire E out;
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M foo (in, out);
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initial begin
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in = A;
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#1 if (out !== A) begin
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$display("FAIL: in=%0d, out=%0d", in, out);
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$finish;
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end
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in = B;
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#1 if (out !== B) begin
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$display("FAIL: in=%0d, out=%0d", in, out);
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$finish;
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end
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$display("PASSED");
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$finish;
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end
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endmodule // main
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module M (input E ei,
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output E eo);
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always_comb eo = ei;
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endmodule // M
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