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https://github.com/steveicarus/iverilog.git
synced 2026-09-07 01:56:52 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
41 lines
839 B
Verilog
41 lines
839 B
Verilog
//
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// Verifies that the PRNG seed streams are unique, well trys anyway.
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//
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module test;
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reg [31:0] rtn;
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reg [31:0] pseed, seed1, seed2;
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reg [31:0] mem1[3:0], mem2[3:0];
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integer i;
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initial begin
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seed1 = 32'hcafe_babe;
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seed2 = 32'hdead_beef;
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// Isolated stream
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for (i = 0; i < 4; i = i + 1) begin
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mem1[i] = $random(seed1);
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end
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// Pull from multiple streams
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seed1 = 32'hcafe_babe;
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seed2 = 32'hdead_beef;
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for (i = 0; i < 4; i = i + 1) begin
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mem2[i] = $random(seed1);
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// pull more values from other pools
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rtn = $random(seed2);
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rtn = $random;
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end
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// Verify the seed1 streams match
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for (i = 0; i < 4; i = i + 1) begin
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if (mem1[i] != mem2[i]) begin
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$display("FAILED %0d: %x != %x", i, mem1[i], mem2[i]);
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$finish;
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end
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end
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$display("PASSED");
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$finish;
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end
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endmodule
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