mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-09-04 08:34:09 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
72 lines
1.4 KiB
Verilog
72 lines
1.4 KiB
Verilog
`timescale 1ns/1ns
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module lfsr_test();
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parameter SIZE = 4;
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reg clk, reset, ena;
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wire [SIZE-1:0] out;
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initial
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begin //{
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clk = 0;
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reset = 0;
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ena = 1'bz;
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#15 reset = 0;
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#20 reset = 1;
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end //}
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initial
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begin //{
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//$dumpfile("lfsr_test.vcd"); // Change filename as appropriate.
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//$dumpvars( 0, lfsr_test);
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$monitor("out=%b", out);
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end //}
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always clk = #10 ~clk;
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lfsr_counter LF( clk, reset, out );
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initial #1000 $finish(0);
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endmodule // gray_code
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module lfsr_counter( clk, reset, out );
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`define W 4
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parameter WIDTH = `W;
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parameter TAP = `W'b1001;
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integer N;
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output [WIDTH-1:0] out;
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input clk, reset;
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wire [WIDTH-1:0] gc;
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reg [WIDTH-1:0] lfsr, next_lfsr;
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reg fb_lsb, fb;
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always @(posedge clk or negedge reset )
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begin //{
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if( reset == 1'b0 )
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lfsr[WIDTH-1:0] <= `W'b0;
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else
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lfsr[WIDTH-1:0] <= next_lfsr[WIDTH-1:0];
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end //}
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always @( lfsr )
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begin //{
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fb_lsb = ~| lfsr[WIDTH-2:0];
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fb = lfsr[WIDTH-1] ^ fb_lsb;
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for( N=WIDTH; N>=0; N=N-1 )
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if( TAP[N] == 1 )
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next_lfsr[N] = lfsr[N-1] ^ fb;
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else
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next_lfsr[N] = lfsr[N-1];
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next_lfsr[0] = fb;
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end //}
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assign out[WIDTH-1:0] = {1'b0, lfsr[WIDTH-1:1]}; //(1)
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//assign out[WIDTH-1:0] = lfsr[WIDTH-1:0]; //(2)
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//assign gc[WIDTH-1:0] = out[WIDTH-1:0] ^ {1'b0, out[WIDTH-1:1]};
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//(3)
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endmodule // gray_counter
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