mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-09-03 08:25:32 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
63 lines
1.7 KiB
Verilog
63 lines
1.7 KiB
Verilog
/*
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* Copyright (c) 2001 Uwe Bonnes
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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`define ADC_DATA_OFFSET 5
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`define ADC_CHANELS 8*48
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//`define ADC_CHANELS 348
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module mymod (out1,out2,state,reset);
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input [8:0] state;
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input reset;
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output out1,out2;
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assign out1 = (state > `ADC_DATA_OFFSET) ? 1 : 0;
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assign out2 = (state > `ADC_CHANELS + `ADC_DATA_OFFSET +1)|| (reset);
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endmodule // mymod
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module t;
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reg [8:0] state;
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reg reset;
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wire out1,out2;
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mymod m1 (out1,out2,state,reset);
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initial
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begin
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//$timeformat(-9,0,"ns",5);
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$display(" TIME:state:out1:out2");
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$monitor("%t:%5d:%4d:%4d",$time,state,out1,out2);
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state =0;
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reset = 0;
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#10
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reset=1;
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#20
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reset=0;
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#5110
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$finish;
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end
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always
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begin
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#10
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if (reset)
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state = 0;
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else
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state=state+1;
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end
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endmodule // t
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