mirror of
https://github.com/steveicarus/iverilog.git
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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
117 lines
1.5 KiB
Verilog
117 lines
1.5 KiB
Verilog
/*
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* Verification test for increment/decrement operators
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*
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* Author: Prasad Joshi <[email protected]>
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*/
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module main;
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logic la;
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logic lb;
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int ia;
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int ib;
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bit ba;
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bit bb;
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real ra;
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real rb;
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real rc;
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initial begin
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/* logic tests */
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la = 0;
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#1
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lb = ++la;
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#1
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if (la != lb) begin
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$display("FAILED");
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$finish;
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end
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ib = 15;
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#1
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ia = ++ib;
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#1
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if (ia != ib) begin
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$display("FAILED");
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$finish;
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end
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ia = 15;
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#1
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ib = ia++;
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#1
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if (ia != 16 || ib != 15) begin
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$display("FAILED");
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$finish;
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end
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ib = --ia;
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if (ib != ia) begin
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$display("FAILED");
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$finish;
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end
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/* bit test */
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ba = 0;
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#1
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for (ia = 0; ia < 10; ia = ia + 1) begin
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bb = --ba;
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#1
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if (bb != ba && !(bb == 1 || bb == 0)) begin
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$display("FAILED");
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$finish;
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end
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end
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/* real decrement test */
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ia = 15;
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ra = --ia;
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if (ra != ia) begin
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$display("FAILED");
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$finish;
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end
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rb = 19.99;
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rc = rb - 2;
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ra = --rb;
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if (ra != rb) begin
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$display("FAILED");
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$finish;
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end
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ra = rb--;
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if (ra == rb || rc != rb) begin
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$display("FAILED");
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$finish;
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end
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/* real increment test */
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ia = 15;
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ra = ++ia;
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if (ra != ia) begin
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$display("FAILED");
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$finish;
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end
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rb = 19.99;
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rc = rb + 2;
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ra = ++rb;
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if (ra != rb) begin
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$display("FAILED");
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$finish;
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end
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ra = rb++;
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if (ra == rb || rc != rb) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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