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Dag Lem
ba7da9d5a5
Internally, the maximum address space of a vector is 31 bits + a sign bit to signal invalid addresses (out of bounds or has one or more x or z bits). This commit ensures that unsigned part-select bit addresses which would otherwise overflow and wrap around within this address space are correctly handled as out of bounds.
26 lines
645 B
Verilog
26 lines
645 B
Verilog
/*
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* partsel_outside_expr
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* Check that base_expr ± bit_number in a part-select does not wrap around
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* within the internal 32 bit (signed) vector address space.
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* This could incorrectly select bits from a vector when unsigned integers
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* are used in the part-select index expression.
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*/
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module main;
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reg [1:0] arr = 1;
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integer unsigned uoffset = -'d1;
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wire [1:0] outside_expr = arr[uoffset +: 2];
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initial begin
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if (outside_expr !== 'x) begin
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$display("FAILED -- non-const base_expr out of bounds value %b != xx", outside_expr);
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$finish;
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end
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$display("PASSED");
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$finish;
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end
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endmodule // main
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