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Lars-Peter Clausen
7f40e120c8
SystemVerilog allows to completely omit the `parameter` or `localparam` keyword in the parameter list. Both at the beginning and before redefining the parameter data type. This is not support in Verilog. Add regression tests that check that this is supported when in SystemVerilog mode. It is not valid to use an implicit data type e.g. just `signed` when `parameter` was omitted, add regression tests to check for this as well. Signed-off-by: Lars-Peter Clausen <[email protected]>
18 lines
458 B
Verilog
18 lines
458 B
Verilog
// Tests that it possible to omit the `parameter` keyword in a parameter port
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// list before changing the parameter type in SystemVerilog. In Verilog this is
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// not allowed and should result in an error.
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module a #(parameter real A = 1.0, integer B = 2);
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initial begin
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if (A == 10.1 && B == 20) begin
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$display("PASSED");
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end else begin
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$display("FAILED");
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end
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end
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endmodule
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module test;
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a #(.A(10.1), .B(20)) i_a();
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endmodule
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