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Lars-Peter Clausen
47e6c71113
In Verilog a parameter in a generate block is invalid and should result in a compile error. In SystemVerilog on the other hand it is valid, but it is equivalent to a localparam and can't be overridden. Add regression tests that check for this. Signed-off-by: Lars-Peter Clausen <[email protected]>
17 lines
298 B
Verilog
17 lines
298 B
Verilog
// Check that it is not possible to override parameters in generate blocks
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module test;
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generate
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genvar i;
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for (i = 0; i < 2; i = i + 1) begin : loop
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parameter A = i;
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reg [A:0] r = A+1;
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end
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endgenerate
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defparam loop[0].A = 10;
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defparam loop[1].A = 20;
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endmodule
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