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Lars-Peter Clausen
37392383b5
Check that scalar typed parameters are handled correctly. Make sure the width of the parameter only depends on the type and not on the value assigned to the parameter. Same for parameters with a 1-bit range specification. Signed-off-by: Lars-Peter Clausen <[email protected]>
27 lines
527 B
Verilog
27 lines
527 B
Verilog
// Check that parameters with a implicit and 1-bit range type are handled correctly
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module test #(
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// This should get truncated to 1'b1
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parameter [0:0] P = 2'b11
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);
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reg failed = 1'b0;
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`define check(expr, val) \
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if (expr !== val) begin \
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$display("FAILED: `%s`, expected %0d, got %0d", `"expr`", val, expr); \
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failed = 1'b1; \
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end
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initial begin
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`check($bits(P), 1);
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`check(P + 1'b1, 1'b0);
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`check(P, 1'b1);
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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