mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-09-03 16:29:25 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
96 lines
2.3 KiB
Verilog
96 lines
2.3 KiB
Verilog
module top;
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// packed 2D array, arranged as 4 bytes of 8 bits each.
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logic [3:0][7:0] word32;
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int idx;
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int x;
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// Show a slice select in a continuous assignment
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wire [7:0] word1 = word32[1];
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initial begin
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// Const slice select in l-values.
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word32[0] = 'h00;
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word32[1] = 'h11;
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word32[2] = 'h22;
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word32[3] = 'h33;
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if (word32 !== 'h33_22_11_00) begin
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$display("FAILED -- word32 = %h (1)", word32);
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$finish;
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end
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#1 if (word1 !== 8'h11) begin
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$display("FAILED -- word1 = %h", word1);
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$finish;
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end
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// Non-constant slice indices, l-value and r-value.
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for (idx = 0 ; idx < 4 ; idx = idx+1)
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word32[idx] = ~word32[idx];
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if (word32 !== ~ 'h33_22_11_00) begin
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$display("FAILED -- word32 = %h (2)", word32);
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$finish;
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end
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word32[0][3:0] = 'h0;
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word32[1][3:0] = 'h1;
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word32[2][3:0] = 'h2;
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word32[3][3:0] = 'h3;
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word32[0][7:4] = 'h3;
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word32[1][7:4] = 'h2;
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word32[2][4 +: 4] = 'h1;
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word32[3][4 +: 4] = 'h0;
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if (word32 !== 'h03_12_21_30) begin
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$display("FAILED -- word32 = %h (3)", word32);
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$finish;
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end
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if (word32[1][7:4] !== word32[1][4 +: 4]) begin
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$display("FAILED -- word32[1][7:4]=%h, word32[1][4 +: 4]=%h",
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word32[1][7:4],word32[1][4 +: 4]);
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$finish;
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end
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x = 4;
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word32[1][x +: 4] = 'h2;
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if (word32[1][7:4] !== word32[1][x +: 4]) begin
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$display("FAILED -- word32[1][7:4]=%h, word32[1][4 +: 4]=%h",
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word32[1][7:4],word32[1][x +: 4]);
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$finish;
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end
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for (idx = 0 ; idx < 8 ; idx = idx+1) begin
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word32[0][idx] = idx[0];
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word32[2][idx] = idx[0];
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word32[1][idx] = ~idx[0];
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word32[3][idx] = ~idx[0];
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end
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if (word32 !== 'h55_aa_55_aa) begin
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$display("FAILED -- word32 = %h (4)", word32);
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$finish;
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end
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for (idx = 0 ; idx < 8 ; idx = idx+1) begin
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if (word32[0][idx] !== word32[2][idx]) begin
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$display("FAILED -- word32[0][%0d]=%b, word32[2][%0d]=%b",
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idx, word32[0][idx], idx, word32[2][idx]);
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$finish;
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end
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if (word32[1][idx] !== word32[3][idx]) begin
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$display("FAILED -- word32[1][%0d]=%b, word32[3][%0d]=%b",
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idx, word32[1][idx], idx, word32[3][idx]);
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$display("FAILED");
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$finish;
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end
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end
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$display("PASSED");
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end
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endmodule
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