mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-09-07 11:51:38 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
94 lines
2.3 KiB
Verilog
94 lines
2.3 KiB
Verilog
/*
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* For a non-blocking delay the last NB assign in the same thread
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* at the same time must set the final result, but you are allowed
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* to have multiple assignments in the queue.
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*/
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module top;
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reg passed = 1'b1;
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reg out;
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real rout;
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integer delay;
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initial begin
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out <= 1'b1;
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out <= 1'b0;
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rout <= 0.0;
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rout <= 1.0;
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#1;
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if (out !== 1'b0) begin
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$display("FAILED: zero delay, expected 1'b0, got %b", out);
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passed = 1'b0;
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end
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if (rout != 1.0) begin
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$display("FAILED: zero delay (real), expected 1.0, got %f", rout);
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passed = 1'b0;
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end
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out <= #1 1'b0;
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out <= #1 1'b1;
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rout <= #1 0.0;
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rout <= #1 2.0;
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#2;
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if (out !== 1'b1) begin
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$display("FAILED: constant delay, expected 1'b1, got %b", out);
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passed = 1'b0;
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end
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if (rout != 2.0) begin
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$display("FAILED: constant delay (real), expected 2.0, got %f", rout);
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passed = 1'b0;
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end
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delay = 2;
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out <= #(delay) 1'b1;
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out <= #(delay) 1'b0;
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rout <= #(delay) 0.0;
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rout <= #(delay) 3.0;
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#(delay+1);
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if (out !== 1'b0) begin
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$display("FAILED: calculated delay, expected 1'b0, got %b", out);
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passed = 1'b0;
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end
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if (rout != 3.0) begin
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$display("FAILED: calculated delay (real), expected 3.0, got %f", rout);
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passed = 1'b0;
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end
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out <= #1 1'b1;
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out <= #3 1'b0;
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out <= #5 1'b1;
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rout <= #1 1.0;
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rout <= #3 3.0;
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rout <= #5 5.0;
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#2;
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if (out !== 1'b1) begin
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$display("FAILED: first delay, expected 1'b1, got %b", out);
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passed = 1'b0;
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end
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if (rout != 1.0) begin
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$display("FAILED: first delay (real), expected 1.0, got %f", rout);
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passed = 1'b0;
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end
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#2;
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if (out !== 1'b0) begin
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$display("FAILED: second delay, expected 1'b0, got %b", out);
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passed = 1'b0;
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end
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if (rout != 3.0) begin
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$display("FAILED: second delay (real), expected 3.0, got %f", rout);
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passed = 1'b0;
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end
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#2;
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if (out !== 1'b1) begin
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$display("FAILED: third delay, expected 1'b1, got %b", out);
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passed = 1'b0;
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end
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if (rout != 5.0) begin
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$display("FAILED: third delay (real), expected 5.0, got %f", rout);
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passed = 1'b0;
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end
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if (passed) $display("PASSED");
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end
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endmodule
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