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By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
175 lines
3.2 KiB
Verilog
175 lines
3.2 KiB
Verilog
//
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// multiply_large.v
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//
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// Copyright (c) 2001 ajb
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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`define W (65) // any value past 32 will suffice
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module multiplier(a,b,sum);
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parameter N=1;
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input[N-1:0] a, b;
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output[N-1:0] sum;
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reg [(N-1)*2:0] tmp;
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integer i;
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always @(a or b)
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begin
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tmp = 0;
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for(i=0;i<N;i=i+1)
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begin
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if(b[i]) tmp=tmp + ({{N{1'b0}}, a} << i);
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end
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end
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assign sum = tmp[N:0];
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endmodule
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module multiply_large;
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reg [0:`W-1] a, b;
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wire [0:`W-1] c, s;
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reg [0:`W-1] d;
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integer i, j;
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reg rc;
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assign c=a*b;
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multiplier #(`W) mpy(a,b,s);
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initial
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begin
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rc=0;
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a={{`W-1{1'b0}}, 1'b1}; // walking 1s
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for(i=0;i<`W;i=i+1)
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begin
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b={{`W-1{1'b0}}, 1'b1};
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for(j=0;j<`W;j=j+1)
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begin
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#1;
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d=a*b;
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if ((c!=d)||(c!=s))
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begin
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$display("a=%h b=%h c=%h d=%h s=%h", a,b,c,d,s);
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rc=1;
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end
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b={b[1:`W-1], 1'b0};
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end
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a={a[1:`W-1], 1'b0};
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end
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a={{`W-1{1'b1}}, 1'b0}; // walking 0s
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for(i=0;i<`W;i=i+1)
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begin
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b={{`W-1{1'b1}}, 1'b0};
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for(j=0;j<`W;j=j+1)
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begin
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#1;
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d=a*b;
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if ((c!=d)||(c!=s))
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begin
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$display("a=%h b=%h c=%h d=%h s=%h", a,b,c,d,s);
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rc=1;
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end
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b={b[1:`W-1], 1'b1};
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end
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a={a[1:`W-1], 1'b1};
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end
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a={{`W-2{1'b0}}, 2'b11}; // walking 11s
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for(i=0;i<`W;i=i+1)
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begin
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b={{`W-2{1'b0}}, 2'b11};
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for(j=0;j<`W;j=j+1)
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begin
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#1;
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d=a*b;
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if ((c!=d)||(c!=s))
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begin
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$display("a=%h b=%h c=%h d=%h s=%h", a,b,c,d,s);
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rc=1;
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end
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b={b[1:`W-1], 1'b0};
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end
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a={a[1:`W-1], 1'b0};
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end
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a={{`W-2{1'b1}}, 2'b00}; // walking 00s
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for(i=0;i<`W;i=i+1)
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begin
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b={{`W-2{1'b1}}, 2'b00};
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for(j=0;j<`W;j=j+1)
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begin
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#1;
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d=a*b;
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if ((c!=d)||(c!=s))
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begin
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$display("a=%h b=%h c=%h d=%h s=%h", a,b,c,d,s);
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rc=1;
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end
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b={b[1:`W-1], 1'b1};
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end
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a={a[1:`W-1], 1'b1};
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end
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a={{`W-3{1'b0}}, 3'b101}; // walking 101s
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for(i=0;i<`W;i=i+1)
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begin
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b={{`W-3{1'b0}}, 3'b101};
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for(j=0;j<`W;j=j+1)
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begin
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#1;
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d=a*b;
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if ((c!=d)||(c!=s))
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begin
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$display("a=%h b=%h c=%h d=%h s=%h", a,b,c,d,s);
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rc=1;
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end
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b={b[1:`W-1], 1'b0};
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end
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a={a[1:`W-1], 1'b0};
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end
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a={{`W-3{1'b1}}, 3'b010}; // walking 010s
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for(i=0;i<`W;i=i+1)
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begin
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b={{`W-3{1'b1}}, 3'b010};
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for(j=0;j<`W;j=j+1)
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begin
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#1;
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d=a*b;
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if ((c!=d)||(c!=s))
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begin
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$display("a=%h b=%h c=%h d=%h s=%h", a,b,c,d,s);
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rc=1;
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end
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b={b[1:`W-1], 1'b1};
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end
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a={a[1:`W-1], 1'b1};
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end
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if (rc) $display("FAILED"); else $display("PASSED");
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$finish;
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end
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endmodule
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