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Martin Whitaker
1fdeb7b982
Also add a test for multiple $monitor task calls and $monitoron and $monitoroff.
39 lines
516 B
Verilog
39 lines
516 B
Verilog
// Test that $monitor correctly cancels a preceding $monitor.
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module test;
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integer a, b;
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initial begin
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a = 0;
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b = 0;
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$monitor("@%0t a = %0d", $time, a);
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repeat (5) begin
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#1;
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a = a + 1;
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b = b + 1;
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end
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$monitor("@%0t b = %0d", $time, b);
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repeat (5) begin
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#1;
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a = a + 1;
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b = b + 1;
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end
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$monitoroff;
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repeat (5) begin
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#1;
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a = a + 1;
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b = b + 1;
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end
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#0;
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$monitoron;
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repeat (5) begin
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#1;
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a = a + 1;
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b = b + 1;
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end
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$finish(0);
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end
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endmodule
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