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Lars-Peter Clausen
99a9be25f0
Check that connections to a module port array with a single element are supported. Signed-off-by: Lars-Peter Clausen <[email protected]>
33 lines
437 B
Verilog
33 lines
437 B
Verilog
// Check that connecting a module port array with a single element is supported
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module M (
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input [7:0] in[0:0],
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output [7:0] out[0:0]
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);
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assign out[0] = in[0];
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endmodule
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module test;
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reg [7:0] A[0:0];
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wire [7:0] B[0:0];
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M i_m (
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.in(A),
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.out(B)
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);
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initial begin
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A[0] = 10;
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#1
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if (B[0] === 10) begin
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$display("PASSED");
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end else begin
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$display("FAILED");
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end
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end
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endmodule
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