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https://github.com/steveicarus/iverilog.git
synced 2026-09-03 16:29:25 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
68 lines
1.5 KiB
Verilog
68 lines
1.5 KiB
Verilog
package fooPkg;
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localparam FOO = 5;
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endpackage
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package barPkg;
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function int get_size (
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input int x
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);
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return x + 3;
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endfunction
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endpackage
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package bazPkg;
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typedef int baz;
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endpackage
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/*
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IEEE 1800-2012 A.1.2 says:
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module_nonansi_header ::=
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{ attribute_instance } module_keyword [ lifetime ] module_identifier
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{ package_import_declaration } [ parameter_port_list ] list_of_ports ;
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module_ansi_header ::=
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{ attribute_instance } module_keyword [ lifetime ] module_identifier
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{ package_import_declaration } [ parameter_port_list ] [ list_of_port_declarations ] ;
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This allows for the importing of packages during module definition which can be used in the
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parameter and port lists.
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*/
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module foo
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// Testing comman separated imports
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import
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fooPkg::*,
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barPkg::*;
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// Testing multiple import statements
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import bazPkg::*;
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#(
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parameter FOO_PARAM = FOO
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)
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(
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input [get_size(7)-1:0] inport
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);
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baz value = 11;
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initial begin
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if ($bits(inport) != 10) begin
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$display("FAILED -- function import in module declaration failed (%d)", $bits(inport));
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$finish;
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end
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if (value != 11) begin
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$display("FAILED -- Something is wrong with typedef import (%d)", value);
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$finish;
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end
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if (FOO_PARAM != 5) begin
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$display("FAILED -- Something is wrong with paramater imports (%d)", FOO_PARAM);
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$finish;
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end
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$display("PASSED");
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$finish;
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end
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endmodule
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