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https://github.com/steveicarus/iverilog.git
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Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
28 lines
453 B
Verilog
28 lines
453 B
Verilog
/*
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* Check simple scope up-reference of memories.
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*/
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module main;
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reg [7:0] foo [0:5];
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integer idx;
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task showstring;
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begin
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for (idx = 0 ; idx < 6 ; idx = idx+1) begin
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$write("%c", foo[idx]);
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end
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$display;
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end
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endtask // showstring
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initial begin
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foo[0] = "P";
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foo[1] = "A";
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foo[2] = "S";
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foo[3] = "S";
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foo[4] = "E";
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foo[5] = "D";
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showstring;
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end
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endmodule // main
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